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MITSUBISHI
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
The M62361FP is a Bi-CMOS semiconductor IC,containing 6 channels of 8-bit D-A converters(DAC),with a buffer operational amplifier provided in the output of each channel.It is easy to use due to serial data input, and three-pin(DT,CK,ST)connection with microcomputer. This IC is designed to be operable when chip select data contained in the 15-bit data conforms to the state of the CS terminal.Accordingly,the IC can process data by strobe signals common with other devices connected to the bus of microcomputer, and does not involve an microcomputer port to drive the IC.The inputs are connected to a level shift circuit so that the input threshold level does not depend on supply voltage.The IC also contains an initialization function to reset output(0 scale)when power is turned ON or drops.
PIN CONFIGURATION (TOP VIEW)
DK CK ST CS NC D.G A.G Vss
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VDD Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 VREF
Outline 16P2N-A
NC:NO CONNECTION
FEATURES
*Output buffer operational amplifier provided in each channel *15-bit serial data input *6 channels of R-2R and segment type 8-bit DAC *Chip select terminal *Power-on reset function
APPLICATION
Digital-analog conversion in industrial or home-use electric equipment. Automatic control in combination with EEROM and microcomputer(Substitute for conventional semi-fixed resistor) Signal gain setting of display monitor and CTV.
BLOCK DIAGRAM
DT CK ST CS
1 15-BIT SHIFT RESISTER 2 3 4
RESET CIRCUIT LEVEL SHIFT
16 VDD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 4
COMPARATOR
6
D.G
8
DECODER
6
9 VREF
8-BIT LATCH 8-BIT DAC 8-BIT LATCH 8-BIT DAC
8-BIT LATCH 8-BIT DAC
8-BIT LATCH 8-BIT DAC
8-BIT LATCH 8-BIT DAC
8-BIT LATCH 8-BIT DAC
8
VSS
7
A.G
15 Ao1
14 Ao2
13 Ao3
12 Ao4
11 Ao5
10 Ao6
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MITSUBISHI
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
EXPLANATION OF TERMINALS
Pin No. 1 2 3 4 16 6 7 9 8 15 14 13 12 11 10 5 Symbol DT CK ST CS VDD D*G A*G VREF Vss Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 NC Function Serial data input terminal Shift clock input terminal to input data at rise of clock pulse Strobe input terminal to latch data in the register when H-level signal is input Chip select terminal Power supply terminal for input level shift circuit and buffer amplifier GND terminal for digital line GND terminal for analog line 8-bit D-A converter power supply terminal 8-bit D-A converter minimum power supply terminal
8-bit D-A converter output terminal
Not used
TIMING CHART (MODEL)
LSB DT D01 D02 D03 D04 D02 D03 D04
CK
ST
AO
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MITSUBISHI
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS(Ta=25C, unless otherwise noted)
Symbol VDD VREF VIN Ao Pd K Topr Tstg Parameter Supply voltage Reference voltage Input voltage Output voltage Power dissipation Thermal derating Operating temperature Storage temperature Conditions Ratings -0.3~+15 -0.3~+8 -0.3~VDD -0.3~VDD 550 5.5 -20~+85 -55~+125 Unit V V V V mW mW/C C C
ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS( Ta=25C,VDD=8.0V,VREF=5.0V,Vss=0V,RL=2k unless otherwise noted)
Symbol VDD IDD VREF Vss IREF RSL EZR EFS DNL ECH VIH VIL IIH IIL VAO Isink Parameter Operating supply voltage Current dissipation Voltage range at VREF Voltage range at Vss Maximum sink current at VREF Resolution Zero point error Full scale error Differential nonlinearity error Error between channels Input voltage Input current Output voltage range Output sink current Output source current Output through rate Reset detection voltage 1 Hysteresis voltage 1 Reset detection voltage 2 Hysteresis voltage 2 Detection of VDD power Detection of VDD power Detection of VREF power Detection of VREF power Set at 15 256 min. for all channels. H-level L-level H-level L-level VDD=6.0 ~ 10V VDD=6.0 ~ 10V VDD=6.0 ~ 10V VDD=6.0 ~ 10V 0.3 0 -5 0.3 4.25 0.05 2.85 0.03 4.45 0.1 3.0 0.06 4.65 0.2 3.15 0.15 Monotony assured Vss0.3V -1.5 -1.5 -1.0 -3 3.5 0 0 -1.5 Set at 107 256 for all channels. Test conditions Ta=-25 ~ +85C Set at 128 256 for all channels. RL= 4.0 -0.2 0.0 1.5 Min. 6.0 Limits Typ. 8.0 5 Max. 14.0 10 7.5 1.0 3 8 1.5 1.5 1 3 VDD 1.0 10 10 VREF -2LSB 100 0 V A mA V/s V V V V Unit V mA V V mA bit LSB LSB LSB LSB V V A A
VREF=VDD-2V
Isource SR VS1 VS1 VS2 VS2
For FSR*,AoFSR-2LSB
(*Full scale range = maximum output voltage setting)
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MITSUBISHI
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
AC CHARACTERISTICS( Ta=25C,VDD=8.0V,VREF=5.0V,Vss=0V,RL=2k unless otherwise noted)
Symbol tCKL tCKH tCR tCF tDCH tCHD tCHS tSTC tSTH tSTD Parameter Clock "L"pulse width Clock "H"pulse width Clock rise time Clock fall time Data set up time Data hold time ST set up time ST hold time ST "H" pulse width Ao output setting time 0 FSR FSR 0 Test conditions Min 200 200 Limits Typ Max Unit ns ns ns ns ns ns ns ns ns s
200 200 300 200 500 500 500 20
TIMING CHART
tCR tCKH tCF
CK tCKL
DT tDCH tCHD tSTH tCHS ST tSTC
tSTD Ao
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MITSUBISHI
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION OF OPERATION 1.Level shift circuit The logical operation in the IC is controlled by VREF voltage. Therefore,the logical level of input is shifted to DG(Low)or VREF(High),regardless of fluctuating VDD. 2.15-bit shift register Data necessary for setting DAC is serially input.The data is input at positive edge of CK signal.The register is capable of retaining 15-bit data consisting of 3 blocks:DAC data.DAC select data and chip select data.
(1)15 bit serial data (LSB) 1 2 DATA (MSB) 9 8
3.Decoder(DAC select decoder) Appropriate one of the 6 DAC channels is selected by the 3bit DAC select data:S01,S02,S03.
S01 0 1 0 1 0 1 0 1 S02 0 0 1 1 0 0 1 1 S03 0 0 0 0 1 1 1 1 VOUT 1 2 3 4 5 6 not select not select
10
11
12
13
14
15
CK (2)Data allocation (LSB) (MSB) :DAC SETTING DATA
4.Comparator(Chip select data) Whether DAC data is effective or not is determined by the 4-bit data(C01 ~ C04)and the logic at CS terminal.Either of the following data combination is required.
C01 0 0 :DAC SELECT DATA C02 0 0 C03 1 1 C04 1 0 CS 0 1
:CHIP SELECT DATA
5.8-bit latch circuit When the data input to shift register meets the above requirement for comparator,D01~D08 data are latched in the channel selected by decoder.This data latching takes place when input at ST terminal is HIGH.
6.8-bit DAC + buffer amplifier Potential difference between VREF and Vss is output with 8bit resolution,using the R-2R system.No resolution is obtained for bit data lower than the output saturated voltage of the buffer amplifiers data lower than the output saturated voltage of the buffer amplifiers of analog output A01 to A06.The minimum value of 300mA,given for the electrical
5
characteristic concerning output voltage range(VAO),indicates that no resolution is secured for output lower than 300mV. For all bit data,resolution is secured when Vss is operated with 300mV or higher voltage.
Ao=
2 0 X D01 + 2 1 X D02 + 22 X D03 + 2 3 X D04 + 24 X D05 + 2 X D06 + 2 X D07 + 2 X D08 * (VREF - Vss) + Vss 256
6
7
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MITSUBISHI
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DAC SETTING DATA(VREF=5.0V,Vss=0V)
(LSB) C01 0 1 0 1 C02 0 C03 0 C04 0 C05 0 C06 0 C07 0 (MSB) C08 0 Vsat A01~A06 0 (15/256) VREF VREF X X (16/256) (17/256)
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
0 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
VREF VREF
X X
(254/256) (255/256)
7.Reset circuit This circuit monitors VDD and VREF,ensuring stable analog output when power is turned ON or OFF.If either input is abnormal,the reset circuit causes output buffer amplifiers to stop operation to retain the output in Vsat state,as well as resetting DAC data(0 scale)of all channels.
If VREF drops earlier than VDD,the analog output reset operation starts at point A.
RESET TIMING CHART
4.45 VDD 4.5 DETECTED (HYSTERESIS VOLTAGE:100mV)
VREF 3.06 (3.0V) 3.0 DETECTED (HYSTERESIS VOLTAGE:60mV)
A AO
t
ALLOWABLE RANGE FOR SETTING OUTPUT
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MITSUBISHI
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
APPLICATION EXAMPLE
VDD=14V max
REGULATOR
16 VREF= 7.5V max 9
VDD VREF Ao1
15 ch1
Ao2 14
ch2
1
DT
Ao3
13
ch3
MICRO COMPUTER
2
CK
Ao4
12
ch4
3
ST
Ao5 11
ch5
4
CS D.G A.G
6 7
Ao6 Vss
8
10
ch6
Vss=0.3~1.0V
When 8 pin is GND,Ao output is 0.3~VREF-1 LSB When 8 pin is Vss,Ao output is Vss~VREF-1 LSB
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MITSUBISHI
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
TYPICAL CHARACTERISTICS(Ta=25C,VDD=8.0V,VREF=5.0V,RL=2k,unless otherwise noted) CURRENT DISSIPATION VS. AMBIENT TEMPERATURE
1.8 1.7 1.6 1.5 1.4 1.3 1.2 -20
8 7 6 5 4 3 2 -20
VREF SINK CURRENT VS. AMBIENT TEMPERATURE
0
20
40
60
80
100
0
20
40
60
80
100
AMBIENT TEMPERATURE Ta(C)
AMBIENT TEMPERATURE Ta(C)
4.6
RESET DETECTION VOLTAGE 1 VS. AMBIENT TEMPERATURE
RESET DETECTION VOLTAGE 2 VS. AMBIENT TEMPERATURE
3.1 4.5 3.0 4.4 2.9 4.3 -20
0
20
40
60
80
100
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE Ta(C)
AMBIENT TEMPERATURE Ta(C)
NONLINEARITY ERROR
0.50 0.40 0.30 0.20 0.10 -0.00 -0.10 -0.20 -0.30 -0.40 -0.50 0 40 80 120 160 200 240 280 DATA
DIFFERENTIAL NONLINEARITY ERROR
0.50 0.40 0.30 0.20 0.10 -0.00 -0.10 -0.20 -0.30 -0.40 -0.50 0 40 80 120 160 200 240 280 DATA
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